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MC10E1651 5V, -5V Dual ECL Output Comparator with Latch
The MC10E1651 is fabricated using ON Semiconductor's advanced MOSAIC IIITM process. The MC10E1651 incorporates a fixed level of input hysteresis as well as output compatibility with 10 KH logic devices. In addition, a latch is available allowing a sample and hold function to be performed. The device is available in both a 16-pin DIP and a 20-pin surface mount package. The latch enable (LENa and LENb) input pins operate from standard ECL 10 KH logic levels. When the latch enable is at a logic high level, the MC10E1651 acts as a comparator; hence, Q will be at a logic high level if V1 > V2 (V1 is more positive than V2). Q is the complement of Q. When the latch enable input goes to a low logic level, the outputs are latched in their present state providing the latch enable setup and hold time constraints are met.
Features http://onsemi.com MARKING DIAGRAMS
16 MC10E1651L AWLYYWW 1 CDIP-16 L SUFFIX CASE 620A 1 20
* * * * * * * * * * * * * * *
Typical 3.0 dB Bandwidth > 1.0 GHz Typical V to Q Propagation Delay of 775 ps Typical Output Rise/Fall of 350 ps Common Mode Range -2.0 V to +3.0 V Individual Latch Enables Differential Outputs 28 mV Input Hysteresis Operating Mode: VCC = 5.0 V, VEE = -5.2 V, GND = 0 V No Internal Input Pulldown Resistors ESD Protection: > 2 kV Human Body Model, > 100 V Machine Model Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V-0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 85 devices Pb-Free Packages are Available*
20 1 PLCC-20 FN SUFFIX CASE 775 A WL YY WW G
MC10E 1651FNG AWLYYWW
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
November, 2006 - Rev. 8
1
Publication Order Number: MC10E1651/D
MC10E1651
Qb LENb 18 Qb GND NC GND Qa 19 20 1 2 3 4 5 6 7 8 20-Lead PLCC (Top View) 17 NC V1b V2b 16 15 14 13 12 11 10 9 VCC NC NC VEE VCC GND Qa Qa LENa V2a V1a VCC VEE 1 GND Qb Qb LENb V1b V2b VCC NC 16 15 14 13 12 11 10 9
16-Pin Ceramic DIP (Top View) 2 3 4 5 6 7 8
Qa LENa NC V2a V1a * All VCC and VCCO pins are NOT tied together on the die. Warning: All VCC, GND, and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. Logic Diagrams and Pinout Assignments
V1a V2a LENa
Qa
Qa
V1b V2b LENb VEE = -5.2 V VCC = +5.0 V
Qb
Qb
Figure 2. Logic Diagram Table 1. PIN DESCRIPTION
PIN Qa, Qa Qb, Qb LENa, LENb V1a, V1b V2a, V2b VCC VEE NC GND FUNCTION ECL Differential Outputs (a) ECL Differential Outputs (b) ECL Latch Enable Input Comparator 1 Input Comparator 2 Positive Supply Negative Supply No Connect Ground
Table 2. FUNCTION TABLE
LEN H H L V1, V2 V1 > V2 V1 < V2 X Function H L Latched
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Table 3. MAXIMUM RATINGS
Symbol VSUP VPP VI Iout TA Tstg qJA qJC VEE Tsol Parameter Total Supply Voltage Differential Input Voltage Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Operating Range Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board GND = 0 V v 3 sec @ 248C v 3 sec @ 260C 28 PLCC 28 PLCC 28 PLCC Continuous Surge Condition 1 |VEE| + |VCC| |V1 - V2| Condition 2 Rating 12.0 3.7 VEE v VI v VCC 50 100 0 to +85 -65 to +150 63.5 43.5 22 to 26 -4.2 to -5.7 265 265 Unit V V V mA mA C C C/W C/W C/W V C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Table 4. DC CHARACTERISTICS VCC = +5.0 V 5%; VEE = -5.2 V 5%, VCC = 0 V (Note 1)
0C Symbol VOH VOL VIL VIH II IIH ICC IEE VCMR Hys Vskew Cin Characteristic Output HIGH Voltage (Note 1) Output Low Voltage (Note 1) Input LOW Voltage (LEN) (Note 1) Input HIGH Voltage (LEN) (Note 1) Input Current (V1, V2) Input HIGH Current (LEN) Positive Supply Current Negative Supply Current Common Mode Range (Note 2) Hysteresis Hysteresis Skew (Note 3) Input Capacitance DIP PLCC 3 2 3 2 3 2 -2.0 27 -1.0 Min -1020 -1950 -1.95 -1.17 Typ Max -840 -1630 -1.48 -0.84 65 150 50 -55 3.0 -2.0 27 -1.0 Min -980 -1950 -1.95 -1.13 25C Typ Max -810 -1630 -1.48 -0.81 65 150 50 -55 3.0 -2.0 30 0 Min -920 -1950 -1.95 -1.07 85C Typ Max -735 -1600 -1.45 -0.735 65 150 50 -55 3.0 Unit mV mV mV mV mA mA V mV mV pF
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input VIL and VIH parameters vary 1:1 with VCC. Output VOH and VOL parameters vary 1:1 with GND. 2. VCMR Min varies 1:1 with VEE; Max varies 1:1 with VCC. 3. Hysteresis skew (Vskew) is provided to indicate the offset of the hysteresis window. For example, at 25C the nominal hysteresis value is 27 mV and the Vskew value indicates that the hysteresis was skewed from the reference level by 1mV in the negative direction. Hence the hysteresis window ranged from 14 mV below the reference level to 13 mV above the reference level. All hysteresis measurements were determined using a reference voltage of 0 mV.
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Table 5. AC CHARACTERISTICS VCC = +5.0 V 5%; VEE = -5.2 V 5%, VCC = 0 V (Note 4)
0C Symbol fMAX tPLH tPHL ts th tpw tskew tJITTER TDE Characteristic Maximum Toggle Frequency Propagation Delay to Output (Note 4) V to Q LEN to Q Setup Time V Enable Hold Time V Minimum Pulse Width LEN Within Device Skew (Note 5) Cycle-to-Cycle Jitter Delay Dispersion (ECL Levels) (Notes 6, 7) (Notes 6, 8) Delay Dispersion (TTL Levels) (Notes 9, 10) (Notes 8, 9) Rise/Fall Times (20-80%) 225 325 475 225 350 100 ps 325 475 250 375 500 100 60 ps 750 550 450 -50 400 15 TBD Min Typ TBD 900 725 300 -250 1050 900 775 550 450 -50 400 15 TBD Max Min 25C Typ > 1.0 925 750 300 -250 1075 900 850 650 550 -100 400 15 TBD Max Min 85C Typ TBD 1025 825 350 -250 1200 1000 ps ps ps ps ps ps Max Unit GHz ps
TDL
tr tf
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Input VIL and VIH parameters vary 1:1 with VCC, output VOH and VOL parameters vary 1:1 with GND. 5. tskew is the propagation delay skew between comparator A and comparator B for a particular part under identical input conditions. 6. Refer to figure 4 and note that the input is at 850mV ECL levels with the input threshold range between the 20% and 80% points. The delay is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q output signals. 7. The slew rate is 0.25 V/NS for input rising edges. 8. The slew rate is 0.75 V/NS for input rising edges. 9. Refer to Figure 5 and note that the input is at 2.5 V TTL levels with the input threshold range between the 20% and 80% points. The delay is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q output signals. 10. The slew rate is 0.3 V/NS for input rising edges.
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APPLICATIONS INFORMATION The timing diagram (Figure 3.) is presented to illustrate the MC10E1651's compare and latch features. When the signal on the LEN pin is at a logic high level, the device is operating in the "compare mode," and the signal on the input arrives at the output after a nominal propagation delay (tPHL, tPLH). The input signal must be asserted for a time, ts, prior to the negative going transition on LEN and held for a time, th, after the LEN transition. After time th, the latch is operating in the "latch mode," thus transitions on the input do not appear at the output. The device continues to operate in the "latch mode" until the latch is asserted once again. Moreover, the LEN pulse must meet the minimum pulse width (tpw) requirement to effect the correct input-output relationship. Note that the LEN waveform in Figure 3. shows the LEN signal swinging around a reference labeled VBBINT; this waveform emphasizes the requirement that LEN follow typical ECL 10KH logic levels because VBBINT is the internally generated reference level, hence is nominally at the ECL VBB level. Finally, VOD is the input voltage overdrive and represents the voltage level beyond the threshold level (VTHR) to which the input is driven. As an example, if the threshold level is set on one of the comparator inputs as 80 mV and the input signal swing on the complementary input is from zero to 100 mV, the positive going overdrive would be 20 mV and the negative going overdrive would be 80 mV. The result of differing overdrive levels is that the devices have shorter propagation delays with greater overdrive because the threshold level is crossed sooner than the case of lower overdrive levels. Typically, semiconductor manufactures refer to the threshold voltage as the input offset voltage (VOS) since the threshold voltage is the sum of the externally supplied reference voltage and inherent device offset voltage.
VBBINT LEN ts V VIN VTHR tPHL Q tPLH(LEN) VOD th tpw
Q
Figure 3. Input/Output Timing Diagram
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DELAY DISPERSION Under a constant set of input conditions comparators have a specified nominal propagation delay. However, since propagation delay is a function of input slew rate and input voltage overdrive the delay dispersion parameters, TDE and TDT, are provided to allow the user to adjust for these variables (where TDE and TDT apply to inputs with standard ECL and TTL levels, respectively). Figure 4 and Figure 5 define a range of input conditions which incorporate varying input slew rates and input voltage overdrive. For input parameters that adhere to these constraints the propagation delay can be described as: TNOM TDE (or TDT)
-0.9 V - 1.07 V INPUT THRESHOLD RANGE - 1.58 V - 1.75 V
where TNOM is the nominal propagation delay. TNOM accounts for nonuniformity introduced by temperature and voltage variability, whereas the delay dispersion parameter takes into consideration input slew rate and input voltage overdrive variability. Thus a modified propagation delay can be approximated to account for the effects of input conditions that differ from those under which the parts where tested. For example, an application may specify an ECL input with a slew rate of 0.25 V/NS, an overdrive of 17 mV and a temperature of 25C, the delay dispersion parameter would be 100 ps. The modified propagation delay would be 775 ps 100 ps
2.5 V 2.0 V INPUT THRESHOLD RANGE 0.5 V 0V
SLEW RATE = 0.25 V/NS SLEW RATE = 0.75 V/NS
SLEW RATE = 0.30 V/NS SLEW RATE = 0.75 V/NS
Figure 4. ECL Dispersion Test Input Conditions
Figure 5. TTL Dispersion Test Input Conditions
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Q Driver Device Q
Zo = 50 W
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = GND - 2.0 V
Figure 6. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device MC10E1651L MC10E1651FN MC10E1651FNG MC10E1651FNR2 MC10E1651FNR2G Package CDIP-16 PLCC-20 PLCC-20 (Pb-Free) PLCC-20 PLCC-20 (Pb-Free) Shipping 25 Units / Rail 46 Units / Rail 46 Units / Rail 500 / Tape & Reel 500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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PACKAGE DIMENSIONS
CDIP-16 L SUFFIX CERAMIC DIP PACKAGE CASE 620A-01 ISSUE O
B
16
A
9
A
M L
B
1 8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. 5 THIS DRAWING REPLACES OBSOLETE CASE OUTLINE 620-10. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
16X
J
E F C K T N G
16X
0.25 (0.010)
M
TB
SEATING PLANE
D
0.25 (0.010)
M
TA
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PACKAGE DIMENSIONS
20 LEAD PLLC CASE 775-02 ISSUE E
B -N- Y BRK D -L- -M- W D V 0.010 (0.250) T L-M N Z 0.007 (0.180) M T L-M U
S
N
S S
0.007 (0.180) M T L-M
N
S
20
1
X VIEW D-D
G1
S
S
S
A Z R
0.007 (0.180) M T L-M 0.007 (0.180) M T L-M
S
N N
S
S
S
H K1
0.007 (0.180) M T L-M
S
N
S
C
E G G1 0.010 (0.250) S T L-M J 0.004 (0.100) -T- SEATING
PLANE
K F VIEW S 0.007 (0.180) M T L-M
S
VIEW S
S
N
S
N
S
NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. DIMENSIONS IN INCHES. 3. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 4. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 5. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 6. DIMENSIONS IN THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10 _ 0.310 0.330 0.040 ---
MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10 _ 7.88 8.38 1.02 ---
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ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC). MOSAIC III is a trademark of Motorola, Inc.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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